datasheet networking clock source ICS650-27 idt? / ics? networking clock source 1 ICS650-27 rev f 051310 description the ICS650-27 is a low cost, low jitter, high performance clock synthesizer for networking applications. using analog phase-locked loop (pll) techniques, the device accepts a 12.5 mhz or 25 mhz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, pci devices, sdram, and asics. the ICS650-27 outputs all have zero ppm synthesis error. the ICS650-27 is pin compatible and functionally equivalent to the ics650-07. it is a performance upgrade and is recommended for all new 3.3v designs. see the mk74cb214, ics551, and ics552-01 for non-pll buffer devices which produce multiple low-skew copies of these output clocks. see the ics570, ics9112-16/17/18 for zero delay buffers that can synchronize outputs and other needed clocks. features ? packaged in 20-pin (1 50 mil) ssop (qsop) ? pb (lead) free package, rohs compliant ? 12.5 mhz or 25 mhz fundamental crystal or clock input ? six output clocks with selectable frequencies ? sdram frequencies of 67, 83, 100, and 133 mhz ? buffered crystal reference output ? zero ppm synthesis error in all clocks ? ideal for pmc-sierra?s atm switch chips ? full cmos output swing with 25 ma output drive capability at ttl levels ? advanced, low-power, sub-micron cmos process ? operating voltage of 3.3 v ? industrial temperature only block diagram clock buffer/ crystal oscillator clock synthesis and control circuitry 25 or 12.5 mhz cyrstal or clock acs1:0 clka1 ccs gnd 2 bcs1:0 2 2 x1/iclk x2 clka2 clkb1 clkb2 clkc1 clkc2 refout vdd 2 /2 /2 oe (all outputs)
ICS650-27 networking clock sour ce clock synthesizer idt? / ics? networking clock source 2 ICS650-27 rev f 051310 pin assignment pin descriptions 13 4 12 5 11 asc1 8 9 10 vdd clkc2 clka2 ccs clkb2 dc 17 16 clkb1 3 x1/iclk vdd clka1 18 refout 1 asc0 x2 bcs0 20 bcs1 19 14 2 7 gnd clkc1 oe gnd 15 6 20-pin (150 mil) ssop pin number pin name pin type pin description 1 acs0 input a clock select 0. selects outputs on clka1 and clka2 per table on page 3. 2 x2 input crystal connection. connect to a fundamental crystal or leave unconnected for a clock input. 3 x1/iclk input crystal connection. connect to a fundamental crystal or clock input. 4 vdd power connect to +3.3 v or 5 v. must be the same as pin 16. 5 acs1 input a clock select 1. selects outputs on clka1 and clka2 per table on page 3. internal pull-up. 6 gnd power connect to ground. 7 clkc1 output output clock c1. depends on setting of ccs per table on page 3. 8 clkc2 output output clock c2. depends on setting of ccs per table on page 3. same as clkc1. 9 clkb2 output output clock b2. depends on setting of bcs1, 0 per table on page 3. 10 clkb1 output output clock b1. depends on setting of bcs1, 0 per table on page 3. 11 ccs input clock c select pin. selects outputs on clkc1 and clkc2 per table on page 3. 12 dc - don?t connect. do not connect anything to this pin. 13 clka2 output output clock a2. depends on setting of acs1, 0 per table on page 3. 14 gnd power connect to ground. 15 oe input output enable. tri-states all outputs when low. internal pull-up. 16 vdd power connect to +3.3 v or 5 v. must be the same as pin 4. 17 clka1 output output clock a1. depends on setting of acs1, 0 per table on page 3. 18 refout output buffered reference clock output. same frequency as crystal or clock input. 19 bcs0 input b clock select 0. selects outputs on clkb1 and clkb2 per table on page 3. 20 bcs1 input b clock select 1. selects outputs on clkb1 and clkb2 per table on page 3. internal pull-up.
ICS650-27 networking clock sour ce clock synthesizer idt? / ics? networking clock source 3 ICS650-27 rev f 051310 for a 25 mhz fundamental cryst al or clock input, the fo llowing four tables apply: a clocks select table (outputs in mhz) c clocks select table (outputs in mhz) b clocks select table (outputs in mhz) reference output clock frequency (in mhz) for a 12.5 mhz fundamental cr ystal or clock i nput, the following four tables apply: a clocks select table (outputs in mhz) c clocks select table (outputs in mhz) b clocks select table (outputs in mhz) reference output clock frequency (in mhz) 0 = connect directly to gnd m = leave unconnected (automatically self biases to vdd/2) 1 = connect directly to vdd asc1 asc0 clka1 clka2 00100off (low) 0 m test test 0175off (low) 1 0 33.3333 16.6667 1 m test test 1 1 66.6667 33.3333 ccs clkc1 clkc2 0 125 125 m test test 17575 bsc1 bsc0 clkb1 clkb2 0 0 te s t te s t 0 m 66.6667 33.3333 0110050 1 0 83.3333 41.6667 1 m te s t te s t 1 1 133.3333 66.6667 refout 25 asc1 asc0 clka1 clka2 0050off (low) 0 m test test 0 1 37.5 off (low) 1 0 16.6667 8.3333 1 m test test 1 1 33.3333 16.6667 ccs clkc1 clkc2 0 62.5 62.5 m test test 1 37.5 37.5 bsc1 bsc0 clkb1 clkb2 0 0 te s t te s t 0 m 33.3333 16.6667 0 1 50 25 1 0 41.6667 20.8333 1 m te s t te s t 1 1 66.6667 33.3333 refout 12.5
ICS650-27 networking clock sour ce clock synthesizer idt? / ics? networking clock source 4 ICS650-27 rev f 051310 external components the ICS650-27 requires a minimum number of external components for proper operation. decoupling capacitor decoupling capacitors of 0.01f must be connected between each vdd and gnd (pins 4 and 6, pins 16 and 14), as close to the device as possible. for optimum device performance, the decoupling capacitor should be mounted on the component side of the pcb. avoid the use of vias in the decoupling circuit. series termination resistor when the pcb trace between the clock outputs and the loads are over 1 inch, series termination should be used. to series terminate a 50 ? trace (a commonly used trace impedance), place a 33 ? resistor in series with the clock line as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . crystal information the crystal used should be a fundamental mode (do not use third overtone), parallel resonant. crystal capacitors should be connected from pins x1 to ground and x2 to ground to optimize the initial accuracy. the value of these capacitors is given by the following equation: crystal caps (pf) = (c l - 6) x 2 in the equation, c l is the crystal load capacitance. so, for a crystal with a 16pf load capacitance, two 20 pf [(16-6) x 2] capacitors should be used. absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ICS650-27. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature -40 to +85 c storage temperature -65 to +150 c junction temperature 175 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature -40 +85 c power supply voltage (measured in respect to gnd) +3.0 +3.3 +3.6 v
ICS650-27 networking clock sour ce clock synthesizer idt? / ics? networking clock source 5 ICS650-27 rev f 051310 dc electrical characteristics unless stated otherwise, vdd = 3.3 v 10% , ambient temperature -40 to +85 c ac electrical characteristics unless stated otherwise, vdd = 3.3 v10% , ambient temperature -40 to +85 c note 1: measured with 15 pf load thermal characteristics parameter symbol conditions min. typ. max. units operating voltage vdd 3.0 3.3 3.6 v input high voltage v ih x1 pin only, clk input vdd/2+1 vdd/2 v input low voltage v il x1 pin only, clk input vdd/2 vdd/2-1 v input high voltage v ih all tri-level type inputs vdd-0.5 v input low voltage v il all tri-level type inputs 0.5 v input high voltage v ih all other inputs 2 v input low voltage v il all other inputs 0.8 v output high voltage v oh i oh = -25 ma 2.4 v output low voltage v ol i ol = 25ma 0.8 v output high voltage, cmos level v oh i oh = -8 ma vdd-0.4 v operating supply current i dd no load 50 ma short circuit current i os each output 50 ma internal pull-up resistor r pu bcs1, oe pins 510 k ? acsi pin 120 k ? nominal output impedance z out 20 ? parameter symbol conditions min. typ. max. units input frequency 10 12.5 or 25 27 mhz output rise time t or 0.8 to 2.0 v, note 1 1.5 ns output fall time t of 2.0 to 0.8 v, note 1 1.5 ns output clock duty cycle at vdd/2, note 1 40 50 60 % frequency error all clocks 0 ppm absolute jitter, short term variation from mean, note 1 150 ps parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 135 c/w ja 1 m/s air flow 93 c/w ja 3 m/s air flow 78 c/w thermal resist ance junction to case jc 60 c/w
ICS650-27 networking clock sour ce clock synthesizer idt? / ics? networking clock source 6 ICS650-27 rev f 051310 package outline and package dimensions (20-pin ssop, 150 mil. body) package dimensions are kept current with jedec publication no. 95 ordering information "lf" suffix to the part number are the pb -free configuration and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature 650r-27ilf 650r-27ilf tubes 20-pin ssop -40 to +85 c 650r-27ilft 650r-27ilf tape and reel 20-pin ssop -40 to +85 c index area 1 2 20 d e1 e seating plane a1 a a2 e - c - b .10 (.004) c c l millimeters inches symbol min max min max a 1.351.75.053.069 a1 0.10 0.25 .0040 .010 a2 -- 1.50 -- .059 b 0.20 0.30 0.008 0.012 c 0.180.25.007.010 d 8.558.75.337.344 e 5.806.20.228.244 e1 3.80 4.00 .150 .157 e 0.635 basic 0.025 basic l 0.401.27.016.050 0 8 0 8
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